The present invention relates to a standard cell used in a semiconductor integrated circuit, a standard cell library, and a semiconductor integrated circuit using it, and particularly relates to a layout structure thereof.
Conventionally, it is widespread to design a semiconductor integrated circuit by combining a plurality of functional blocks, generally called standard cells, of which height, source wiring structure, and the like are uniformed.
In association with miniaturization of semiconductor integrated circuits in recent years, a problem of variation in final dimension of various patterns arises. Especially, variation in final dimension of gates of transistors affects transistor characteristics severely. Specifically, drive strength of a transistor lowers as gate length of the transistor increases and the drive strength thereof increases as the gate length thereof reduces. When the drive strength varies, the characteristics of a standard cell vary to cause variation in characteristics of a semiconductor integrated circuit, lowering yield and reliability of the semiconductor integrated circuit.
One of factors in variation in final dimension of the transistor gates is irregularity of gate patterns. This will be explained below with reference to FIG. 8. FIG. 8 is a plan view showing one example of a conventional standard cell. As shown in FIG. 8, a conventional standard cell 800 includes: a semiconductor layer 801; a source wiring 802 provided at one end of the semiconductor layer 801; a ground wiring 803 provided at another end of the semiconductor layer 801 which faces the source wiring 802; p-type diffusion regions 804, 805 provided in the semiconductor layer 801; n-type diffusion regions 806, 807 provided in the semiconductor layer 801; gates 808, 809, 810, 811 (only a part overlaid with a diffusion region is referred to as a gate in the present description) provided on the p-type diffusion regions 804, 805; and gates 812, 813, 814, 815 provided on the n-type diffusion regions 806, 807. Herein, the p-type diffusion regions 804, 805 and the gates 808, 809, 810, 811 provided thereon compose p-channel transistors Tr808, Tr809, Tr810, Tr811, respectively, while the n-type diffusion regions 806, 807 and the gates 812, 813, 814, 815 provided thereon compose n-channel transistors Tr812, Tr813, Tr814, Tr815, respectively.
The p-channel transistor Tr808 and the p-channel transistor Tr809, for example, share the diffusion region. And some other adjacent transistor pairs share the diffusion regions. Wherein, contact vias for electrically connecting the diffusion regions, the wiring layers, and a substrate, inter-cell wirings, input/output pins, and the like, which are not shown, are provided in the standard cell 800, in addition to the elements shown in the drawing.
In the standard cell 800 shown in FIG. 8, the respective sides of the gates of the p-channel transistors 808 to 811 and of the n-channel transistors 812 to 815 are as follows in detail.    (1) No gate exists on the left side of the gate 808 of the p-channel transistor Tr808 and the gate 809 is provided on the right side thereof with a spacing S1.    (2) The gates 808, 810 are provided on the right and left sides of the gate 809 with the spacing S1, respectively.    (3) The gate 809 is provided on the left side of the gate 810 with the spacing S1 while the gate 811 is provided on the right side thereof with a spacing S2 (S2>S1).    (4) The gate 810 is provided on the left side of the upper part of the gate 811 with the spacing S2 and no gate is provided on the left side of the lower part thereof while no gate is provided on the right side thereof.    (5) No gate is provided on the left side of the gate 812 of the n-channel transistor Tr812 and the gate 813 is provided on the right side thereof with a spacing S3 (S3<S1).    (6) The gates 812, 814 are provided on the right and left sides of the gate 813 with the spacing S3, respectively.    (7) The gate 813 is provided on the left side of the gate 814 with the spacing S3 while the gate 815 is provided on the right side thereof with a spacing S4 (S4>S2).    (8) The gate 814 is provided on the left side of the upper part of the gate 815 with the spacing S4 and no gate is provided on the left side of the lower part thereof while no gate exists on the right side thereof.
As described above, the layout conditions of the gates 808 to 811 and the gate 812 to 815 are different from one another, and this is one of factors in variation in final gate dimension, that is, variation in characteristics of the standard cells.
As a conventional technique for overcoming this disadvantage, Japanese Patent Application Laid Open Publication No. 9-289251A has been proposed. FIG. 9 is a plan view showing the structure of a conventional standard cell of disclosed in Japanese Patent Application Laid Open Publication No. 9-289251A. A standard cell 900 shown in FIG. 9 includes: a source wiring 902; a ground wiring 903 provided apart from the source wiring 902 with a semiconductor layer 901 interposed therebetween; a p-type diffusion region 904 provided in the semiconductor layer 901; a n-type diffusion region 905 provided in the semiconductor layer 901; gates 906 to 912 provided on the p-type diffusion region 904; and gates 913 to 919 provided on the n-type diffusion region 905.
Out of the gates 906 to 912 and 913 to 919, the gates 907 to 909 and 911 compose p-channel transistors Tr907 to Tr909 and Tr911 in combination with the p-type diffusion region 904, respectively, while the gates 914 to 916 and 918 compose n-channel transistors Tr914 to Tr916 and Tr918 in combination with the n-type diffusion region 905, respectively.
The gates 906, 910, 912 are extended to the source wiring 902 to be connected thereto respectively through contact vias 920, 921, 922, so as to be in the OFF state. The gates 913, 917, 919 are extended to the ground wiring 903 to be connected to the ground wiring 903 through respective contact vias 923, 924, 925, so as to be in the OFF state.
In the standard cell 900 in FIG. 9, the intervals of the gates on the diffusion regions, which are irregular in the standard cell in FIG. 8, are set to be regular intervals and the transistors in the OFF state are arranged at regular intervals of the gate intervals instead of providing independent diffusion regions. As a result, the gates 907 to 911 and 914 to 918 are arranged adjacent to one another with the same spacing S1. This improves the irregularity in gate intervals, compared with the standard cell 800 shown in FIG. 8, to minimize difference in pattern density, suppressing variation in final gate dimension and variation in characteristics of the standard cell.
As another conventional technique for improving the irregularity in patterns of gates, Japanese Patent Application Laid Open Publication No. 2002-26125A has been proposed. FIG. 10 is a plan view showing a structure of a conventional standard cell disclosed in Japanese Patent Application Laid Open Publication No. 2002-26125A. A standard cell 1000 shown in FIG. 10 includes: a source wiring 1002; a ground wiring 1002 provided apart from the source wiring 1002 with a semiconductor layer 1001 interposed therebetween; p-type diffusion regions 1004, 1005 provided in the semiconductor layer 1001; n-type diffusion regions 1006, 1007 provided in the semiconductor layer 1001; gates 1009 to 1011, and 1013 provided on the p-type diffusion regions 1004, 1005; gates 1016 to 1018, and 1020 provided on the n-type diffusion regions 1006, 1007; dummy gates 1008, 1012, 1014 provided on the respective sides of the p-type diffusion regions 1004, 1005 in the semiconductor layer 1001; dummy gates 1015, 1019, 1021 provided on the respective sides of the n-type diffusion regions 1006, 1007 in the semiconductor layer 1001.
Out of the gates, the gates 1009 to 1011, and 1013 compose p-channel transistors Tr1009 to Tr1011, and Tr1013 in combination with the p-type diffusion regions 1004, 1005 while the gates 1016 to 1018, and 1020 compose n-channel transistors Tr1016 to Tr1018, and Tr1020 in combination with the n-type diffusion regions 1006, 1007.
On the other hand, the dummy gates 1008, 1012, 1014, 1015, 1019, and 1021 are provided in a region other than the diffusion regions of the semiconductor layer 1001 and do not contribute to operation of the transistors.
In the standard cell 1000 in FIG. 10, the intervals of the gates on the diffusion regions, which are irregular in the standard cell in FIG. 8, are set to be regular and the dummy gates are provided among the gates at the same intervals as those of the gates. As a result, the gates 1009 to 1011, and 1013 and the gates 1016 to 1018, and 1020 are arranged adjacent to other gates and dummy gates with the same spacings.
Further, the gate width of the dummy gate 1012 arranged on the left side of the gate 1013 is set larger than that of the gate 1013 so that a dummy electrode is formed over the entirety on the left side of the gate 1013 with the spacing S1. The same is applied to the gate 1020. With this arrangement, the gate irregularity is further improved and the variation in final gate dimension is further suppressed, further suppressing the variation in characteristics of the standard cell.
Japanese Patent Application Laid Open Publication No. 2002-26125A discloses another conventional technique for improving the irregularity in pattern of gates. FIG. 11 is a plan view showing a structure of a conventional standard cell disclosed in Japanese Patent Application Laid Open Publication No. 2002-26125A. Difference of the standard cell shown in FIG. 11 from the standard cell shown in FIG. 10 is that the gate length of the dummy dates 1112, 1119 is larger than that of the other gates and dummy gates. In this example, also, the irregularity in gates and dummy gates is improved to suppress the variation in final gate dimension and the variation in characteristics of the standard cell.
However, in the case where there is irregularity in gate length (for example, some of gates or dummy gates is larger) even with the intervals of the adjacent gates uniformed as described above, final gate dimension varies to cause drive strength of the transistors to vary and to cause the characteristics of the standard cell to vary. None of the aforementioned conventional techniques refers to the case where there is a transistor composing the function of the standard cell that has gate length larger than that of the other transistors, nor to the variation in characteristics of the standard cell to be suppressed in such the case.
Transistors having larger gate length are used for lowering its drive strength in some cases. For example, in a standard cell of a circuit which has an input A and an output Y and which is composed of four inverters 1031 to 1304 as shown in FIG. 12A, the gate length of some gates of the inverters composing the standard cell is set larger for comparatively larger delay between the input A and the output Y. Also, a standard cell of a circuit which has an input A and which is composed of two inverters 1305, 1306 as shown in FIG. 12B has a bus holding function for holding a value of the input A. In this standard cell, the gate length may be set larger for lowering the drive strength of the inverter 1306 that drives the input A. In addition, referring to a standard cell of a flip-flop circuit FF having inputs of a data input D, a scan data input DT, a scan enable signal NT, and a clock signal CK, and outputs of a data output Q and a scan data output SQ, as shown in FIG. 13, there are many cases where the standard cell is connected to another flip-flop for sending/receiving scan data, which is liable to cause hold time violation. In order to restrain the hold time violation, a delay in taking data from the scan data input DT or in outputting data to the scan data output SQ is increased by increasing the gate length of transistors connected to the scan data input DT and the scan data output SQ in some cases.
Moreover, a size of a standard cell is defined by an integral multiple of a unit length (grid), in general. In this case, the width of the standard cell must be an integral multiple of the grid and this may cause the gate length of dummy gates provided on the edge of the standard cell to be different from that of the other gates. For example, if the width of the conventional standard cell 1000 shown in FIG. 10 is not in an integral multiple of the grid, it is necessary to increase the width of the standard cell to an integral multiple by increasing the gate length of the dummy gates 1008, 1015, 1014, and 1021. If the dummy gates on the edge of the standard cell are shared among adjacent standard cells, variation in final dimension is caused in the gate of the transistor in the adjacent standard cell adjacent to the dummy gates to cause variation in drive strength of the transistors, causing variation in characteristics of the standard cell.